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Computer and peripheral devices
Informationpresent on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW
VCC: Input voltage (3 : 9v)
thus no external antenna coil is needed
The axis is enclosed with static sealing
74HC161 ( Presettable synchronous 4-bit binary counter-asynchronous reset) Micro SD Card Computer and peripheral devicesIntroduction : 74HC161 is a synchronous presettable binary counter with an internal look head carry. Synchronous operation is provided by having all flip flops clocked simultaneously on the positive going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at thedata inputs (D0 to D3) to be loaded into the counter on the